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职位列表


 

Digital IC Design/Verification Engineer

Description

  • As a team member to design and verification next-generation Mixed-Signal Communication SoC
  • Digital IC design from RTL to netlist including synthesis, timing constraint composing, DFT, ECO
  • Digital IC design including synthesis, verification, algorithm implementation, etc.
  • Program development in TCL/Python/... to improve productivity

Qualifications

  • BS/MS in ME, EE or CS.
  • Positive, active, self-motivated and teamwork
  • 2+ years of hands-on experience in IC design industry
  • Experiences on Cadence, Synopsys, Mentor EDA tools
  • Real tape-out experience is a good plus
  • Familiar with UVM verification methodology is a plus
  • Experiences on verification on FPGA and familiar with FPGA EDA tools is a plus
  • Familiar with HW/SW interface, any CPU ISA like RISC-V/ARM/MIPS/... is a plus
  • Network/Communication System/DSP/Mixed-Signal/Automotive design experience is a plus

 

Software Engineer

Description

  • As a team member to development software or firmware for High performance communication SoC
  • Design, develop, test, deploy, maintain and improve software or firmware

Qualifications

  • BS degree in Computer Science, similar technical field of study or equivalent practical experience.
  • Must be proficient in at least one programming language, include but not limited to C/C++/Python/Java/JS/Lua/Go/...
  • Manage individual project priorities, deadlines and deliverables
  • Positive, active, self-motivated and teamwork
  • Interest and ability to learn other coding languages as needed.
  • Experience working with one or more from the following are preferred:
    • Bare-metal or RTOS development with C or assembly language
    • Application or driver development on linux based operating system
    • Network Knowledge or Internet Protocol
    • DSP Algorithm or Communication System

 

Senior Analog IC Design Engineer

Job Descriptions

  1. Design high performance analog circuit, including high resolution ADC, high linearity and low noise amplifier, high linearity and low noise analog filter; low noise PLL, low noise OSC, low noise LDO, low noise voltage/current reference etc.
  2. Plan and perform silicon engineering validation of the responsible circuit. Perform silicon debug. Work with test engineer to plan and determine ATE test plan for the responsible circuit

Qualifications

  1. Master degree in electrical engineering with 5 years of experience or more, PhD in electrical engineer with 3 years of experience or more.
  2. Strong experience in high resolution ADC design, or low noise PLL design or high linearity and low noise amplifier/analog filter design
  3. Solid understanding of analog design fundamentals including device physics, analog circuit analysis, sampling theory and control theory. Good understanding of communication theory.
  4. Strong analytical skill and familiar with underline theory for both time domain analysis and frequency domain analysis
  5. Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, floor planning, sensitive signal routing, current density and reliability considerations.
  6. Familiar with both schematic and layout tool, methodologies, flow and CAD tools such as SPICE, Cadence virtuoso, Spectre, PCELL layout, Calibre physical verification.
  7. Good team work, responsible, good communication skill.

 

Senior Analog IC Layout Engineer

Job Descriptions

  • Work with analog designer to perform high performance analog circuit layout, including high performance PLL, ADC/DAC, Amplifier, BandGap, regulators, high speed I/O etc.
  • Work with analog designer in module layout floor planning, integration.
  • Work with project lead to do full chip floor planning, full chip integration, DRC/LVS/ERC verification, and tape out.

Qualifications

  • BS with 5 years of experience or more IC analog layout experience. BS in electrical engineering is preferred.
  • Good understanding of IC process fundamental, Good knowledge of electrical circuit theory.
  • Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, sensitive signal routing, current density and reliability considerations.
  • Familiar with layout methodologies, flow and CAD tools such as Cadence virtuoso, PCELL layout, Calibre physical verification.
  • Prefer experience with Place and Route, full chip SOC integration, tape out.
  • Good team work, follow analog designer requirement and guardian, good communication skill.

 

Analog IC Layout Engineer

Job Descriptions

  • Work with analog designer to perform high performance analog circuit layout, including high performance PLL, ADC/DAC, Amplifier, BandGap, regulators, high speed I/O etc.
  • Work with analog designer in module layout floor planning, integration.
  • Work with project lead to do full chip floor planning, full chip integration, DRC/LVS/ERC verification, and tape out.

Qualifications

  • BS with 1 years of experience or more. BS in electrical engineering is preferred.
  • Good understanding of IC process fundamental, Good knowledge of electrical circuit theory.
  • Solid understanding and experience in key analog layout considerations such as device matching, parasitic, noise coupling, sensitive signal routing, current density and reliability considerations.
  • Familiar with layout methodologies, flow and CAD tools such as Cadence virtuoso, PCELL layout, Calibre physical verification.
  • Prefer experience with Place and Route, full chip SOC integration, tape out.
  • Good team work, follow analog designer requirement and guardian, good communication skill.